FPGA Flappy Bird Game
(November 2025) Designed and implemented a Flappy Bird-style game on the DE1-SoC FPGA using SystemVerilog with FSM-based game control, clock division, and input debouncing for EE 271 Digital Logic course.
Overview
As the final project for EE 271: Digital Logic at the University of Washington, I designed and implemented a Flappy Bird-style game on the DE1-SoC FPGA. The project showcased proficiency in digital design, hardware control logic, and real-time embedded systems.
Course Information
EE 271: Digital Logic | University of Washington | Final Project
Technologies & Tools
SystemVerilogFPGA (DE1-SoC)FSM-based DesignHardware Control LogicModelSim SimulationDigital Logic Design
Key Features & Implementation
- ✓FSM-based game control system managing game states (idle, playing, game over)
- ✓Clock division circuits for precise timing control
- ✓Input debouncing for reliable button press detection
- ✓Real-time hardware control logic for gameplay mechanics
- ✓LED and 7-segment display outputs for visual feedback
- ✓Verified functionality through ModelSim simulation and on-board FPGA testing
Outcomes & Impact
- ✓Delivered a fully functional design that met all project requirements
- ✓Received full credit for correctness, robustness, and implementation quality
- ✓Successfully demonstrated real-time hardware control and game logic on physical FPGA
- ✓Gained hands-on experience with FPGA development workflow from simulation to deployment